A packet-processing device, like a switch microchip, generally operates by inputting packets, storing the packet data, processing a portion of the packet data and modifying and/or outputting the packet data based on the processing. The device comprises a datapath memory (or packet memory) of a datapath subsystem that is used to store/buffer the packet data while the packet is being processed and a control path memory (or search memory) of a control path subsystem used to store the data used to process the packet. However, often these two subsystems are independent such that each is only able to use its own memory regardless of how the memory of the other subsystem is being utilized. As a result, this independent memory partition between the two subsystems can lead to overall memory usage inefficiency of the device if one of the subsystems does not need all the memory space available in its memory but the other subsystems could use more memory space than it is available in its memory. For example, if the switch device is deployed close to the edge of a processing network (e.g. data center network), it is expected that more packet buffering within the datapath memory and fewer search tables within the control path memory are needed. On the contrary, if the device is deployed close to the core of the network, the opposite may be true. Thus, the efficiency of the use of memory on the device is not optimized.